Low drop-out (LDO) voltage regulators find applications in integrated circuits where voltage regulation is desired. For example, LDO voltage regulators may be used to supply less than the maximum voltage to selected sections or components of an integrated circuit. An example environment where LDO voltage regulators may be deployed, includes multiprocessors or multi-core processing systems comprising two or more processors or processing cores. Each core may be configured for operating frequencies or processing capabilities specific to the core, and so the power characteristics (e.g., power consumption at desired operating frequencies) of the cores may vary. For example, a core which is to be operated at its maximum performance or highest frequency may be provided the maximum voltage supply, whereas the voltage supply can be reduced for a core which is operated at a lower performance/frequency. LDO voltage regulators may be used to supply a voltage (also referred to as a regulated voltage, herein) that is less than the maximum voltage to some cores based on their individual power characteristics.
FIG. 1 illustrates a conventional multi-core processing system 100 comprising two or more cores depicted as cores 102a-m. Power head switches 106a-m can be closed or turned on in order to supply maximum supply voltage (VDD 108) to the respective cores 102a-m, for example, in cases where the respective cores 102a-m are to be operated at their maximum performance/frequency. Where a lower performance/frequency is acceptable for one or more cores, their corresponding power head switches 106a-m are opened or turned off, and LDO voltage regulators 104a-m are used to provide lower, regulated voltages to those cores. Thus, by controlling power head switches 106a-m and LDO voltage regulators 104a-m, lower voltages may be supplied to the cores. In this manner, energy consumption of multi-core processing system 100 can be reduced.
LDO voltage regulators 104a-m are designed to provide high bandwidths to enable fast responses to fast variations in current demands (or “di/dt,” as known in the art), while mitigating voltage droops which are detrimental to the performance or speed of corresponding cores 102a-m. In order to support the current demands, LDO voltage regulators 104a-m may be designed with large headroom voltages. However, low headroom voltages are desirable in some situations, which are difficult to achieve in conventional designs of LDO voltage regulators. Related characteristics of conventional LDO voltage regulators are explained with reference to FIG. 2.
FIG. 2 illustrates a detailed view of an example design of any one of LDO voltage regulators 104a-m. Reference voltage Vref 202 is received at one input of operational amplifier 204, whose output is coupled to the gate of p-channel or p-type metal oxide semiconductor (PMOS) transistor 206. The supply voltage VDD 108 (from FIG. 1) supplies input voltage Vin 208 for LDO voltage regulators 104a-m, and output voltage Vout 210 is the regulated voltage that is supplied to the corresponding cores. Output voltage Vout 210 is also fed back at another input of operational amplifier 204. Input voltage Vin 208 and output voltage Vout 210 appear at source and drain terminals of PMOS transistor 206, respectively. Corresponding cores 102a-m for LDO voltage regulators 104a-m are also shown.
The headroom of LDO voltage regulators 104a-m is the difference between input voltage Vin 208 (which, as will be recalled, is the maximum voltage which supports the highest performance/speed of the corresponding cores) and the desired output voltage Vout 210 (which corresponds to the voltage which supports a lower performance/speed of the corresponding cores which are not operated at their maximum performance/operating frequency). It is observed that making the headroom smaller provides more states of dynamic voltage and frequency scaling (DVFS), which leads to better energy optimization of multi-core processing system 100. As seen from above, the headroom, Vin 208 minus Vout 210, represents the drain to source voltage (Vds) of PMOS transistor 206.
Referring now to FIG. 3, plot 300 is shown, where plot 300 is a graphical representation of the variation of load current 312 of any one of cores 102a-m of FIG. 1, as a function of headroom or Vds 310 of its corresponding LDO voltage regulator 104a-m. With reference to FIG. 2, it is seen that a minimum voltage output from operational amplifier 204 corresponds to a maximum gate to source voltage (Vgs) of PMOS transistor 206. Plots 302, 304, 306, and 308 represent variations of load current 312 with headroom or Vds 310 for various values of Vgs (respectively, for Vgs=1V, 0.8V, 0.6V, and 0.4V in the example illustrated). As previously mentioned, it is desirable to achieve high numbers of DVFS states, which may entail reducing the headroom or Vds 310.
Considering PMOS transistor 206, for a particular width of PMOS transistor 206 and a particular value of Vgs (e.g., any one of plots 302-308), PMOS transistor 206 may supply the desired load current 312 of the corresponding core when Vds 310 is greater than a minimum value. As the width of PMOS transistor 206 increases, this minimum value of Vds 310 decreases. However constraints such as available area and bandwidth of LDO voltage regulators 102a-m, may impose restrictions on increasing the widths of corresponding PMOS transistors 206.
Given the limited sizes and widths of PMOS transistor 206 in conventional LDO voltage regulators 104a-m, reducing Vds 310 puts PMOS transistor 206 deeper in the active region of PMOS transistor 206 (e.g., corresponding to values of Vds 310 falling between voltage 314 and voltage 316 in FIG. 3). For these low values of Vds 310 between voltages 314 and 316, the corresponding load current 312 (indicated by currents 315 and 317, respectively) passing through PMOS transistor 206 is very sensitive to supply noise, due to the steeper slope of the load current 312 versus Vds 310 in these regions. Further, such low values of load current 312 may not satisfy the current demands of the corresponding cores. Thus, lowering Vds 310 to voltages 314-316 can lead to a voltage supply droop, which is detrimental to performance of the corresponding core. Hence, it may not be possible to lower the headroom voltage or Vds 310 to desired levels in conventional LDO voltage regulators 104a-m. 
Accordingly, the headroom voltages or values of Vds 310 for conventional LDO voltage regulators 104a-m tend to be higher than desired. In other words, it may be difficult to increase Vout 210 to be closer than a certain amount to Vin 208, referring back to FIG. 2. This means that in conventional implementations, cores 102a-m which can be operated at an intermediate voltage value (wherein the intermediate voltage value falls between Vin 208 and the maximum value of Vout 210 that is possible), will end up being operated at the maximum voltage Vin 208 (e.g., by turning on corresponding power head switches 106a-m and avoiding the use of LDO voltage regulators 104a-m). Accordingly, one or more cores 102a-m may end up being operated at a higher voltage value (maximum voltage Vin 208) even though it may be possible to operate these one or more cores 102a-m at a lower voltage (the intermediate voltage value), due to restrictions on how much the headroom voltages Vds 310 of their corresponding LDO voltage regulators 104a-m can be lowered. Thus, power and energy consumptions of these one or more cores 102a-m may also be seen to correspondingly increase.
As seen from the above discussion, lower headroom voltages are desirable but may not be possible to achieve in conventional LDO voltage regulators.